This invention relates to the field of semiconductor assembly, and more particularly to an interconnection method and structure for a semiconductor device.
A semiconductor device in its most common form comprises a semiconductor die having bond pads thereon, a lead frame mechanically connected with the die, bond wires which electrically couple the bond pads with lead fingers of the lead frame, and encapsulation material which surrounds the die, the bond wires, and the majority of the lead frame. The device is electrically coupled with a printed circuit board (PCB) by soldering leads of the lead frame with pads on the PCB.
While increasing the speed and improving the reliability of components such as microprocessors, memory, and logic devices are goals of designers, the design described above has elements that are contrary to optimal component speed and reliability. For example, each bond wire is connected at two points, one connection to a bond pad and one connection to a lead finger of the lead frame. These connections are subject to separation, for example from pressure exerted on the bond wire during the encapsulation process resulting from lead sweep. Further, the connection may be adequate during testing but the bond wire can separate from the die or the lead frame during shipment or while in use from various failure mechanisms. Finally, the signal path provided by conventional package designs is relatively long which decreases signal speed and integrity and thereby increases the signal delay.
Another source of malfunction for semiconductor devices is the mechanical attachment between the die and the lead frame. The die rests on a die paddle in a typical package or is attached to lead fingers overlying the die in a leads-over-chip package. In either case separation of the die from the lead frame can occur, for example from thermal mismatch between the silicon die and the metal lead frame which stresses an attachment material that mechanically connects the die with the lead frame.
Another disadvantage of the design described above is that while it can be manufactured to produce a relatively thin package, for example in a thin small outline package (TSOP), an encapsulated semiconductor device requires a relatively large surface area of the PCB onto which it is installed. As miniaturization of electronics is typically a design goal, the semiconductor device described above does not lend itself to providing a small assembly.
A method and structure for providing an interconnection for communication with a semiconductor device which reduces or eliminates the problems described above would be desirable.
The present invention provides a new method and structure which reduce problems associated with the manufacture of semiconductor devices, particularly problems resulting from poor bond wire connections and problems associated with lead frames. In accordance with one embodiment of the invention, a semiconductor device is provided which comprises a semiconductor wafer section (which can include an entire wafer or a portion thereof) having a major surface with a plurality of conductive pads thereon and a plurality of elongated electrical interconnections having first and second ends. The first end of each interconnection is formed to contact one of the pads. The device further comprises a dielectric encasing the electrical interconnections wherein at least a portion of the major surface is encased in dielectric. The second end of each the electrical interconnection is free from dielectric.
The end which is free from dielectric provides a contact point for attachment to an electronic device, for example through a printed circuit board. Thus the lead frame is eliminated and the interconnection which contacts the bond pad can be directly electrically coupled with the printed circuit board.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.